1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a structure for data input and output in a dynamic type semiconductor memory device having a plurality of data input/output pins.
2. Description of the Background Art
FIG. 1 shows a structure of a general data processing system. Referring to FIG. 1, a data processing system includes a data processor 900 of, for example, a CPU (Central Processing Unit), a DRAM (Dynamic Random Access Memory) 920 as an external memory device, and a DRAM controller 910 for controlling the access from data processor 900 to DRAM 920.
DRAM controller 910 includes an address multiplexer 912 for multiplexing an address signal provided from data processor 900 on an address bus 921a into a row address signal and a column address signal, and providing the same to DRAM 920 via an address bus 921b, a data buffer 914 for carrying out buffering of data transfer between data processor 900 and DRAM 920, and a control driver 916 for generating and providing to DRAM 920 via a control bus 923b a control signal required for driving DRAM according to a control signal provided from data processor 900 on a control bus 923a. Data buffer 914 carries out data transmission/reception with data processor 900 via a data bus 922a, and carries out data transmission/reception with DRAM 920 via a data bus 922b.
Control driver 916 provides a wait signal to CPU 900 via control bus 923a when DRAM 920 is not accessible due to carrying out, for example, an automatic refresh operation.
FIG. 2 schematically shows a structure of a conventional DRAM used as DRAM 920 of FIG. 1. In FIG. 2, a structure of a 4M-bit DRAM is shown with four data input/output terminals (referred to as "IO pin" hereinafter).
Referring to FIG. 2, a 4M-bit DRAM includes a memory cell array 57 having a plurality of dynamic type memory cells 57a arranged in a matrix of 1024 (=2.sup.10) rows.times.4096 (=2.sup.2 .multidot.2.sup.10) columns. In memory cell array 57, a word line WL is provided corresponding to each row of memory cells. A pair of bit lines BL and /BL is arranged corresponding to one column of memory cells 57a.
The 4M-bit DRAM further includes a row address buffer 52 for receiving an external address signal Ai (i=0-9) for generating complementary row address signals RAi and /RAi, a row decoder 53 for decoding row address signals RAi and /RAi from row address buffer 52 to select a corresponding word line in memory cell array 57, a sense amplifier group 58 having a sense amplifier SA provided corresponding to each column (each bit line pair) of memory cell array 57 for detecting and amplifying data of a memory cell connected to a selected word line by row decoder 53, a column address buffer 55 for receiving an externally applied address signal Ai for generating complementary column address signals CAi and /CAi, a column decoder 56 for decoding a predetermined address signal bit from column address buffer 55 to select a corresponding column in memory cell array 57, and an I/O control circuit 59 for selecting a column according to a predetermined column address signal bit from column address buffer 55 out of the columns selected by column decoder 56 for carrying out data reception/transmission with the selected column.
Column decoder 56 receives column address signal bits CA2-CA9 and /CA2-/CA9 from column address buffer 55. Because there are 4096 columns in memory cell array 57, column decoder 56 selects a bit line pair provided corresponding to 16 columns in memory cell array 57 by a column address signal of 8 bits.
Control circuit 59 further selects 4 columns out of the 16 columns selected by column decoder 56 according to column address signal bits CA0, /CA0, CA1 and /CA1 from column address buffer 55. I/O control circuit 59 transmits internal write data DIO0-DI03 to the selected 4 columns when a write control signal WD from a write control signal generation circuit 63 which will be described afterwards is activated.
The DRAM further includes an input circuit 64 for input of data, an output circuit 61 for providing data, a write control signal generation circuit 63 for controlling data input and output, and a /RAS buffer 51 and a /CAS buffer 54 for controlling the write control signal generation circuit 63 and internal operation of this DRAM.
/RAS buffer 51 receives an externally applied row address strobe signal ext /RAS to provide an internal row address strobe signal /RAS. Internal row address strobe signal /RAS is used to activate the circuit associated with row selection inside the DRAM. In FIG. 2, internal row address strobe signal /RAS is indicated as to be applied only to row address buffer 52. Row address buffer 52 responds to activation of internal row address strobe signal /RAS to latch an external address signal Ai, and to provide row address signals RAi and /RAi.
/CAS buffer 54 receives an external column address strobe signal ext /CAS to generate an internal column address signal /CAS. Internal column address strobe signal /CAS provides the latching and generating timing of a column address signal in column address buffer 55, and also controls the input and output operation of data.
Output control signal generation circuit 60 receives an internal column address strobe signal /CAS from /CAS buffer 54 and an externally applied output enable signal /OE to generate an output control signal OD when both of these two signals attain an activated state of a low level. Output control signal OD attains a high level at the time of activation.
Write control signal generation circuit 63 receives a column address strobe signal /CAS from /CAS buffer 54 and an externally applied write enable signal /WE to generate and provide to I/O control circuit 59 a write control signal WD having a constant pulse width when both the two signals attain an activated state of a low level. Write control signal WD attains a high level at the time of activation.
Output circuit 61 includes output buffers 61a-61d activated in response to an output control signal OD from output control signal generation circuit 60 to provide to IO pins 62a-62d data DQ0-DQ3 of logics respectively corresponding to internal output data DO0-DO3 of 4 bits provided from I/O control circuit 59.
Input circuit 64 includes input buffers 64a-64d for receiving at IO pins 62a-62d external write data DQ0-DQ3 to provide in parallel internal write data DI0-DI3 of logics corresponding to these external write data to I/O control circuit 59. Next, the operation of the 4M-bit DRAM of FIG. 2 will be described.
First, a data reading operation will be described with reference to the operation waveform diagram of FIG. 3.
An address signal Ai (i=0-9) corresponding to a row address is provided from an external source. At time t1 when an external row address strobe signal ext /RAS falls to a low level of an activated state, an internal row address strobe signal /RAS provided from /RAS buffer 51 attains an activated state of a low level. In response to internal row address strobe signal /RAS of an activated state, row address buffer 52 latches an address signal Ai to provide row address signals RAi and /RAi.
Row decoder 53 decodes row address signals RAi and /RAi from row address buffer 52 to select a word line corresponding to a row address in memory cell array 57 according to the decoded result. The data of the memory cell array connected to the selected word line WL is read out onto a corresponding bit line. Then, sense amplifier SA in sense amplifier group 58 is activated, whereby the potential of a corresponding bit line pair is amplified differentially.
In parallel to this row selection and sensing operation, output enable signal /OE provided to output control signal generation circuit 60 attains a low level of an activated state at time t2. At this time point, internal column address strobe signal /CAS is not activated, so that output control signal OD provided from output control signal generation circuit 60 maintains a low level of a deactivated state.
An address signal Ai (I=0-9) corresponding to a Y address (column address) is applied. Then, an external column address strobe signal ext /CAS falls to a low level of an activated state at time t3. In response, internal column address strobe signal /CAS generated from /CAS buffer 54 attains a low level of an activated state. In response to an internal column address strobe signal /CAS of an activated state, column address buffer 55 latches an address signal Ai to provide column address signals CAi and /CAi. Column decoder 56 decodes column address signal bits CA2, /CA2-CA9, /CA9 to select 16 pairs of bit lines in memory cell array 57.
The data of the 16 pairs of bit lines selected by column decoder 56 are provided to I/O control circuit 59, whereby the data of 16 bits is amplified by a preamplifier not shown.
I/O control circuit 59 further selects 4 bits out of the 16-bit data amplified by the preamplifier according to the logics of column address signal bits CA0, /CA0, CA1 and /CA1 from column address buffer 55. The data of 4 bits are amplified by a main amplifier in I/O control circuit 59 to be transmitted to output buffers 61a-61d in output circuit 61 as internal output data DO-DO3.
Output control signal generation circuit 60 raises output control signal OD to a high level of an activated state when internal column address strobe signal /CAS becomes activated at time t3. In response, output buffers 61a-61d in output circuit 61 are enabled, whereby data DO0-DO3 transmitted from I/O control circuit 59 are buffered and provided in parallel to IO pins 62a-62d as data DQ0-DQ3.
A data writing operation will be described hereinafter with reference to FIG. 4. Write data DQ0-DQ3 are provided to IO pins 62a-62d. Input buffers 64a-64d in input circuit 64 provide to I/O control circuit 59 internal data DI0-DI3 of logics corresponding to write data DQ-DQ3 applied to IO pins 62a-62d.
Here, an address signal Ai (i=0-9) corresponding to an X address (row address) is provided from an external source. When external row address strobe signal ext /RAS attains a low level of an activated state at time t1, row address buffer 52 latches an address signal Ai to provide internal row address signals RAi and /RAi. According to row address signals RAi and /RAi, a corresponding word line in memory cell array 57 is selected by row decoder 5.
At time t2, write enable signal /WE attains an activated state of a low level. Here, write control signal WD provided from write control signal generation circuit 63 maintains the low level of a deactivated state since internal column address strobe signal /CAS is not yet activated.
An address signal Ai (i=0-9) corresponding to a Y address (column address) is applied. Then, at time t3, an external column address strobe signal ext /CAS falls to a low level of an activated state. In response, internal column address strobe signal /CAS provided from /CAS buffer 54 attains a low level of an activated state. Column address buffer 55 latches the address signal Ai to provide column address signals CAi and /CAi. Column decoder 56 decodes column address signals CA2, /CA2-CA9, /CA9 to select 16 pairs of bit lines in memory cell array 57, whereby these 16 pairs of bit lines are connected to I/O control circuit 59.
At time t3 when internal column address strobe signal /CAS attains an activated state, write control signal WD provided from write control signal generation circuit 63 rises to a high level of an activated state for a predetermined time. In response to this write control signal WD of an activated state, I/O control circuit 59 decodes column address signals CA0, /CA0, CA1 and /CA1 from column address buffer 55 to transmit respectively internal write data DI0-DI3 provided from input buffers 64a-64d to 4 pairs of bit lines out of the 16 bit line pairs.
When external row address strobe signal ext /RAS rises to a high level, and external column address strobe signal /CAS rises to a high level at time t4, one memory cycle is completed.
As described above, signals /RAS and /CAS must be pulled down to a low level of an activated state to access a DRAM. When an external row address strobe signal ext /RAS once attains a deactivated state of a high level, external row address strobe signal ext /RAS cannot be pulled down to a low level until the elapse of a time period called a RAS precharge time tRAS. This is to reliably precharge the potential of a bit line or the like to a predetermined potential. Therefore, there is a problem that a DRAM cannot be accessed at high speed.
A possible consideration to implement a high speed memory system is to provide in parallel a plurality of DRAMs to reduce the access time effectively by sequentially accessing these plurality of DRAMs.
FIG. 5 shows an embodiment of such a memory system structure. Referring to FIG. 5, a memory system includes a memory #A925a and a memory #B925b provided in parallel with a data bus 922. A processor 926 is connected to data bus 922. Processor 926 is not limited to a CPU and may be a data processor such as a DSP (Digital Signal Processor). An address is applied to memories #A925a and #B925b in common via an address bus 921. Similarly, a signal /RAS defining a memory cycle is also applied. Separate input/output control signals .phi.RW1 and .phi.RW2 are provided to memory #A925a and memory #B925b, respectively. Signals /RAS, .phi.RW1 and .phi.RW2 are transmitted on a control bus 923. Input/output control signals .phi.RW1 and .phi.RW2 correspond to respective combinations of signals /RAS, /WE, and /OE.
When signals .phi.RW1 and .phi.RW2 attain a low level of an activated state, data input/output with respect to memory #A925a and memory #B925b is allowed. The operation of the memory system of FIG. 5 will be described hereinafter with reference to an operation waveform diagram shown in FIG. 6.
With signal /RAS attaining an activated state of a low level and memories #A925a and #B925b attaining an operational state, an internal row selecting operation is executed. Then, input/output control signal .phi.RW1 is pulled down to a low level of an activated state, and memory #A925a is accessed to carry out input or output of data DQA. Input/output control signal .phi.RW1 is rendered to a deactivated state of a high level, simultaneous to the fall of input/output control signal .phi.RW2 to an activated state of a low level. Then, data input/output with respect to memory #B925b is executed.
Data of memory #A925a and data of memory #B925b will appear continuously on data bus 922, so that data input/output can be executed at high speed without being affected by a RAS precharging time.
In the structure shown in FIG. 5, toggling of a column address strobe signal /CAS such as in a page mode operation is not required, and access can be carried out more rapidly than in a page mode. In page mode, a column address strobe signal /CAS is toggled while row address strobe signal /RAS maintains a low level of an activated state as shown in FIG. 7. In response to signal /RAS attaining an activated state, a row address signal is latched to select one row in the DRAM array. In response to the transition of signal /CAS to an activated state, a column address signal is fetched to carry out a column selecting operation in a DRAM array. Because a different column address signal is fetched for each toggle of signal /CAS, data reading or writing is executed of a memory cell corresponding to each column address. FIG. 7 shows an example where data reading is carried out. In such a page mode, there is a CAS access time of tCAS starting from the fall of signal /CAS up to the output of a valid data. Because input/output control signals .phi.RW1 and .phi.RW2 include a signal /CAS in the memory system of FIG. 5, there exists CAS access time for each of memories #A and #B. However, the toggle of column address strobe signal /CAS can be excluded effectively to eliminate the transition time of signal /CAS to a high level, resulting in access at high speed.
In a memory system, an error detection circuit for ensuring reliability of data is provided. A parity bit is generally used for error detection. A bit of "0" or "1" is added so that the number of "1" in the data becomes an even number or an odd number. This additional bit is called a parity bit.
FIG. 8 schematically shows a structure of a memory system including error checking functionality. Referring to FIG. 8, a memory system includes a data memory 930 for storing data, a parity bit memory 932 for storing a parity bit corresponding to each data stored in data memory 930, and a parity checking circuit 934 for generating a parity bit and carrying out error detection. An address signal and a control signal are applied to data memory 930 and parity bit memory 932 via an address bus 933 and a control bus 935.
Data memory 930 carries out data transmission/reception with data bus 931. FIG. 8 shows an embodiment where data bus 931 has a width of 8 bits. Data generally has a byte as the minimum unit, and one parity bit is added to a 8-bit data.
In data writing operation, parity checking circuit 934 generates one bit of parity bit from the data of 8 bits on data bus 931 to write the same into parity bit memory 932. In data reading, parity checking circuit 934 receives data of 8 bits from data memory 930 read out on data bus 931 and a parity bit read out from parity bit memory 932 to make determination whether the number of "1"s included in the data bits and the parity bit is an even number (or an odd number). An error flag is generated according to this determination to indicate whether an error bit is included in the data bit. The operation of parity checking circuit 934 will be described briefly with reference to FIGS. 9 and 10.
The operation of the parity checking circuit in data writing will be described with reference to FIG. 9. In general, a write enable signal /WE is pulled down to an activated state of a low level prior to column address strobe signal /CAS (early write cycle). In response to write enable signal /WE (applied via control bus 935), parity checking circuit 934 fetches the write data on data bus 931 to generate a parity bit PB. When column address strobe signal /CAS attains an activated state of a low level, write data D and parity bit PB are written into data memory 930 and parity bit memory 932, respectively.
The operation of data reading will be described with reference to FIG. 10. Following the activation of signal /CAS to a low level, data bit Q from data memory 930 and parity bit PB from parity bit memory 932 attain an ascertained state after an elapse of a predetermined time. Using these data bits of the valid state, parity checking circuit 934 counts the number of "0"s (or "1"s) included therein to make determination whether an error bit is included in data bit Q according to the counted result. When signal /CAS attains a deactivated state of a high level, an error flag from parity checking circuit 934 is decided.
By using the above-described parity checking circuit 934, an error in a data bit can be checked to form a memory system of high reliability.
FIG. 11 shows a specific structure of a memory system including conventional parity checking functionality. Referring to FIG. 11, the memory system includes first and second memory groups 10 and 30 connected parallel to a data bus 20 of a width of 16 bits.
First memory group 10 includes two memory sub-groups 12 and 13. Second memory group 30 includes two memory sub-groups 32 and 33.
Memory sub-group 12 includes 4M-bit DRAMs 12a and 12b, each including four IO pins 11. Memory sub-group 13 includes 4M-bit DRAMs 13a and 13e, each including four IO pins 11. Each IO pin 11 of DRAMs 12a and 12b of memory sub-group 12 is connected to control buses 20a and 20b of a width of 4 bits. IO pins 11c and 11d of DRAMs 13a and 13b are connected to control buses 20c and 20d, respectively, of a width of 4 bits.
Memory sub-group 32 includes 4M-bit DRAMs 32a and 32b having four IO pins 31a and 31b, respectively. Memory sub-group 33 includes 4M-bit DRAMs 33a and 33b having four IO pins 31c and 31d, respectively. IO pins 31a, 31b, 31c and 31d are connected to control buses 20a, 20b, 20c and 20d, respectively.
Write enable signal /WE, output enable signal /OE, external row address strobe signal ext /RAS, and an address signal are provided in common to DRAMs 12a, 12b, 13a, 13b, 32a, 32b, 33a, and 33b. External column address strobe signal ext /CAS0 is applied to DRAMs 12a and 12b of memory sub-group 12. External column address signal ext /CAS1 is applied to DRAMs 13a and 13b of memory sub-group 13. External column address strobe signal ext /CAS2 is applied to DRAMs 32a and 32b of memory sub-group 32. External column address strobe signal ext /CAS3 is applied to 4M-bit DRAMs 33a and 33b of memory sub-group 33.
According to the above-described structure, control of data input/output can be carried out in the units of memory sub-groups, i.e. in the units of 8 bits.
The memory system further includes a parity bit memory 40 having 1M-bit DRAMs 42a, 42b, 42c and 42d provided corresponding to memory sub-groups 12, 13, 32 and 33. 1M-bit DRAMs 42a-42d respectively include one of IO pins 41a-41d. In FIG. 11, a parity checking circuit for generating a parity bit and carried out parity checking is indicated simply by blocks 43a, 43b, 43c and 43d. A control signal similar to that provided to corresponding memory sub-group is applied to parity checking circuits 43a and 43d. For the sake of simplification, this signal path and the data input/output path are not shown.
A control signal similar to that applied to a corresponding memory sub-group is provided to each of 1M-bit DRAMs 42a, 42b, 42c and 42d. The operation will be described briefly hereinafter.
First, the operation of providing data of 16 bits from memory group 10 will be described. Here, external row address strobe signal ext /RAS attains an activated state of a low level. Therefore, 4M-bit DRAMs 12a, 12b, 13a, 13b, 32a, 32b, 33a and 33b latch an applied address signal as a row address signal. Similarly, in parity bit memory 40, 1M-bit DRAMs 42a-42d latch a row address signal.
Then, external column address strobe signals ext /CAS0 and ext /CAS1 provided to first memory group 10 attain an activated state, and DRAMs 12a, 12b, 13a, 13b in memory group 10 latch an address signal as a column address signal.
In second memory group 30, external column address strobe signal ext /CAS2 and ext /CAS3 both maintain the deactivated state of a high level. Therefore, although 4M-bit DRAMs in second memory group 30 execute a column selecting operation, an output high impedance state is maintained since an output control signal is not generated as shown in FIG. 2.
When output enable signal /OE attains an activated state of a low level, data of 16 bits are provided on data bus 20 from first memory group 10 via IO pins 11a-11d. Simultaneously, a parity bit is provided from 1M-bit DRAMs 42a and 42b in parity memory circuit 40. Parity checking circuits 43a and 43b check whether the number of "1"s in the data of 8 bits is an even number (or an odd number) on the basis of the parity bit provided from 1M-bit DRAMs 42a and 42b, and the data provided from memory sub-groups 12 and 13. An error flag is set according to this checking result.
Next, the operation of writing data of 16 bits into memory group 10 will be described hereinafter. Similar to data reading, an external row address strobe signal ext /RAS and external column address strobe signals ext /CAS0 and ext /CAS1 are applied to memory group 10. External column address strobe signals ext /CAS2 and ext /CAS3 maintain the high level of a deactivated state for memory group 30. As a result, data writing to memory group 30 is inhibited.
When write enable signal /WE and external column address strobe signals ext /CAS0 and ext /CAS1 both attain an activated state of a low level, data of 16 bits on data bus 20 are written into 4M-bit DRAMs 12a, 12b, 13a and 13b in memory group 10. Parallel to this writing operation, parity checking circuits 943a and 943b respond to write enable signal /WE to generate a parity bit of "1" or "0" according to the number of "1" included in the data applied on data bus 20. In memory circuit 40, 1M-bit DRAMs 42a and 42b both attain a writing state, and parity bits generated from parity checking circuits 943a and 943b are written via IO pins 41a and 41b.
The reading and writing operation of data with respect to memory group 30 is similar to that of the first memory group 10. In this case, data input/output is inhibited in memory group 10, i.e. external column address strobe signals ext /CAS0 and ext /CAS1 both attain a deactivated state of a high level. Parity checking circuits 943c and 943d carry out parity checking at the time of writing a parity bit and reading out data with respect to 1M-bit DRAMs 42c and 42d.
In the memory system of FIG. 11, 4 DRAMs of a x1 organization is used for parity bit storage. The four DRAMs 42a-42d are activated simultaneously by external row address strobe signal ext /RAS and execute an operation related to row selection. However, the input/output of a parity bit is actually carried out only by two DRAMs and power is wasted. Furthermore, because four DRAMs are used, the circuit complexity of parity bit memory 40 is increased to become a bottleneck in forming a memory system of a small level.
An approach of using one 4M-bit DRAM (1M.times.4-bit DRAM) in a parity bit memory 40 is considered as shown in FIG. 12 to solve the above-described problem.
Referring to FIG. 12, a parity bit memory 40 includes one 4M-bit DRAM 43. 4M-bit DRAM 43 has a structure similar to a 4M-bit DRAM used in memory groups 10 and 30 for data bit storage. Parity bit memory 40 further includes a 4-input NAND circuit 44 for receiving external column address strobe signals ext /CAS0, ext /CAS1, ext /CAS2 and ext /CAS3, and an inverter circuit 45 for inverting an output of NAND circuit 44. An external column address strobe signal ext /CAS corresponding to 4M-bit DRAM 43 is generated from inverter circuit 45.
The structures of memory groups 10 and 30 are similar to those shown in FIG. 11. In FIG. 12, the parity checking circuit is not explicitly shown for the sake of simplification. NAND circuit 44 provides a signal of a high level when external column address strobe signal ext /CASk (k=0-3) attains an activated state of a low level, and column address strobe signal ext /CAS generated from inverter circuit 45 attains an activated state of a low level.
Parity bit memory 43 has a structure shown in FIG. 2. When column address strobe signal ext /CAS provided from inverter circuit 45 attains an activated state of a low level, data reading to IO pins 41a-41d and writing data applied to IO pins 41a-41d to selected memory cells are carried out. In this case, the following problem will occur.
For the sake of simplifying the explanation, it is assumed that a parity checking circuit is provided for each memory sub-group as shown in FIG. 13. More specifically, parity checking circuits 943a-943d are provided for memory sub-groups 12, 13, 32, and 33, respectively. Memory sub-groups 12 and 32 share a 8-bit data bus 20A, and memory sub-groups 13 and 33 share a 8-bit data bus 20B. A logic gate 46 shown in FIG. 13 includes NAND circuit 44 and inverter circuit 45 shown in FIG. 12.
The case is considered where data is to be written into memory sub-groups 12 and 13. Here, writing data to memory sub-groups 32 and 33 is inhibited. Parity checking circuits 943a and 943d execute a parity bit generation operation in response to a write enable signal /WE. Here, parity checking circuits 943a and 943c generate a parity bit from the data on 8-bit data bus 20A, and parity checking circuits 943b and 943d generate a parity bit from the 8 bit data on 8-bit data bus 20B. The parity bits generated by parity checking circuits 943a-943d are attained in response to the fall of external column address strobe signal ext /CASi to a low level. The parity bits generated by parity checking circuits 943a-943d are written in parallel to parity bit memory 43.
Here, the parity bits generated by parity checking circuits 943c and 943d are parity bits irrelevant of data written into memory sub-groups 32 and 33. Therefore, there is a problem that an erroneous parity bit is written into parity bit memory 43. Similar to a DRAM, when the outputs of parity checking circuits 943a-943d attain an ascertained state from a high impedance state in response to the fall of external column address strobe signal ext /CASi, the outputs of parity checking circuits 943c and 943d attain a high impedance state. Therefore, uncertain data of a high impedance state will be written into parity bit memory 43. Similarly, an erroneous parity bit data is written.
The data reading operation will next be described. A case is considered where data of memory sub-groups 12 and 13 are read out. Here, parity bits of 4 bits are applied from parity bit memory 43 to parity checking circuits 943a-943d. Parity checking circuits, 943a and 943b carries out error checking of a parity bit according to the data read out from memory sub-groups 12 and 13 and the parity bit provided from parity bit memory 43. In this case, proper error checking can be carried out. Parity checking by parity checking circuits 943c and 943d are not required. This means that parity bits not required are provided from parity bit memory 43. (All the output buffers in the output circuit shown in FIG. 2 operate in parallel). Therefore, there is a problem of increase in consumption power in parity bit memory 43.
When a parity checking circuit is provided for each 8-bit data bus instead of the structure of FIG. 13, and the connection between a parity checking circuit and a data bus is switched according to an external column address strobe signal ext /CASk (k=0-3), the IO pins of parity bit memory 43 attain a high impedance state in writing data to de-selected memory sub-groups, resulting in uncertain data being written. In reading out data, unrequired parity bits will be provided on signal lines attaining a high impedance state from the IO pins corresponding to the de-selected memory sub-group. Therefore, the above-described problem will occur in either case.